3 binary inputs mean there are 8 different combinations of inputs and for each combination of input, there is a separate output line to respond. This decoder has 3 binary inputs and 8 output lines. This decoder produces “0” on a separate output line, for a specific binary input combination. Implementation of these expression using NAND gates is shown in the figure below. It can be designed with NAND gate considering the output of the decoder will be invert of AND gate decoder.ĭ̅ 0 = A̅B̅, D̅ 1 = A̅B, D̅ 2 = AB̅, D̅ 3 = AB Min-terms are products of the input, which means that decoder is made up of AND gate and NOT gates. In other words, the data may be decoded by decoders same like data encoded by encoders in term of reverse operation. It actually converts coded information in one format to another format. Active low when enable input is low the decoder is enabled. Active high when enable input is high the decoder is enabled when its low the circuit is disabled. Enable can be active high and active low. There is an enable input which can enable and disable the whole circuit. In simple words, Binary Decoder used to decode a Binary Codes and it is the reverse of Binary Encoders. 74137 TTL 3 to 8 Line Decoder with Pin ConfigurationsĪ digital combinational circuit used for converting “ n” bits of binary number into a combination of “ 2 n” or less unique and separate output lines is called digital decoder or binary decoder.Binary Decoder IC Configuration & Pinouts.3 to 8 Line Decoder Using 2 to 4 Line Decoder.Construction of 2 to 4 Line Decoder Using NAND Gates.Half Adder Implementation Using Decoder.Construction of 2 to 4 Line Decoder using AND Gate.
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